An example of the flow of the inspection process in the manufacturing process of a semiconductor device carried out after forming semiconductor circuits on a semiconductor wafer (hereinafter, simply referred to as a wafer) is shown in FIG. 51 with using a package product, a bare chip, and CSP (Chip Size (Scale) Package), which are typical shipping forms of semiconductor devices, as examples.
In the manufacturing process of the semiconductor device, roughly three inspections described below are carried out as shown in FIG. 51. The first is a wafer inspection carried out in the wafer state in which the semiconductor circuits and electrodes are formed on a wafer to check the conduction state and the electrical signal operating state of the semiconductor elements, the second is a burn-in inspection in which semiconductor elements are placed at a high temperature or high-voltage applied state to extract unstable semiconductor elements, and the third is a sorting inspection to check the product performance before shipping the semiconductor devices.
With respect to the apparatus (semiconductor inspection apparatus) used in such inspections of semiconductor devices, in conventional technologies, many semiconductor devices (semiconductor chips (hereinafter, simply referred to as chips)) are provided on the surface of a wafer, and they are individually separated for use. Many electrodes are disposed in an array on the surface of each of the individually separated semiconductor devices. When a large number of such semiconductor devices are industrially produced and the electrical characteristics thereof are inspected, a connecting device comprising probes formed of tungsten needles obliquely projecting from a probe card is used. The inspection by the connecting device employs the method in which contact is achieved by scrubbing the electrodes with the contact pressure utilizing the flexure of the probes so as to inspect the electrical characteristics thereof.
Recently, along with the density growth of semiconductor elements, in the inspection process in the manufacture of semiconductor devices, the pitches of the probes for inspection have been narrowing, and the number of pins of the probes has been increasing. Therefore, it has been desired to develop an inspection apparatus of semiconductor elements using a connecting device capable of reliably transmitting electrical signals between the electrodes of the semiconductor elements and inspection circuits, probing minute electrodes of the semiconductor elements having narrow pitches and many pins with high precision in the step of carrying out an operation inspection and further probing the semiconductor elements with a low load so as to prevent damages.
As the inspection method and inspection apparatus that enable characteristic inspections of semiconductor elements in the case where the density of the semiconductor elements is grown, the pitches thereof are narrowed and an operation test by high-speed signals is required, there are the technologies described in the collection of papers of ITC (International Test Conference), 1988, pp. 601 to 607 (Non-Patent Document 1). FIG. 52 is a schematic diagram of the structure of the inspection apparatus disclosed in the Non-Patent Document 1, and FIG. 53 is an enlarged perspective view showing the principal part of the inspection apparatus. In a probe for semiconductor inspection used herein, wiring 202 is formed by photolithography techniques on an upper surface of a flexible insulating film 201, a ground layer 203 is formed on a lower surface of the insulating film 201, and semispherical bumps 205 formed by plating at through holes 204 of the insulating film 201 which are provided at the positions corresponding to the electrodes of a semiconductor to be inspected are used as contact terminals. This technology employs the method in which the bumps 205 connected to inspection circuits (not shown in the drawings) via the wiring 202 formed on the surface of the insulating film 201 and via a wiring board 206 are brought into contact with the electrodes of the semiconductor elements to be inspected by scrubbing the bumps 205 with the elastic force of a plate spring 207, thereby mutually transmitting signals to carry out the inspection.
Japanese Patent Application Laid-Open Publication No. 2005-24377 (Patent Document 1) discloses inspection apparatus of semiconductor elements, and FIG. 54 is a schematic view of the structure of a probe card for the inspection thereof. In this probe apparatus, a probe sheet is divided into four, and pyramidal contact terminals 212 and an insulating film 213 on which wiring is formed are pressed down by a spring plunger 211 provided at the center of the probe sheets via a pressing piece 214 and a buffer material.
Also, Japanese Patent Application Laid-Open Publication No. 07-283280 (Patent Document 2) discloses an inspection system in which contact terminals are formed by using the holes, which are formed by performing selective anisotropic etching to a silicon wafer, as molds, the contact terminals are electrically connected to wirings formed in a flexible insulating film, a probe sheet fixing board is fixed to the rear surface of the insulating film reverse to the contact terminal disposed surface of the insulating film via a buffer layer, the probe sheet fixing board is superimposed on a wafer supporting substrate on which a wafer having semiconductor devices to be inspected formed thereon is fixed to a wafer-shaped groove, and the distal-end plane of the contact terminal group and the plane of the electrodes of the wafer are brought into contact with each other, thereby achieving electrical connection and carrying out an inspection of the semiconductor devices.
Further, Published Japanese Translation of PCT Application No. 2002-531915 (Patent Document 3) discloses a spring contact element formed by lithography techniques. FIG. 55 is a schematic diagram showing an intermediate stage of a manufacturing process of the spring contact element formed by the lithography techniques. In this process, a tip part (contact terminal) 217 is formed by using a hole 216, which is formed by performing anisotropic etching to a silicon substrate 215, as a mold, a beam part (beam) 218 and a post part 219 connected to the tip part 217 are formed by the lithography techniques and surface polishing processing (Chemical Mechanical Polishing: CMP), the post part 219 is connected to an electrode 221 of a ceramic multi-layer wiring board 220 by solder 222, and lastly, the tip part 217 is removed from the silicon substrate 215.